(a) Field of the Invention
This invention relates to the manufacturing method of semiconductor devices such as insulated gate transistors, junctioned gate field effect transistors, bipolar transistors, etc.
(b) Prior art
Further miniaturization of transistors is being promoted every year in response to increased requirements of higher speed and higher integration of devices. In this trend, the self-aligning technique is necessary, in addition to miniature processing techniques. For example, by the manufacturing method of bipolar transistors, namely Super Self-Alignment Technology, described in Electronics Letters, Volume 19, P283-P284 (issued in 1983), 30 picosec, of propagation delay time was achieved. According to this method, locations and size of p-type active base, p+ base region and n+ emitter are defined by one selective etching of polysilicon film in the size of the emitter region, and this method has an advantage that the width of the p+ base region is defined by the amount of side-etching and is very narrow. However, a significant problem with this method is that many processes, such as four polysilicon depositions and two isotropic etchings, are required. A manufacturing method related to an MOS transistor is described in Tsushin Gakkai Denshi Gijutsu Kenkyu Hokoku (Research Report of Electronics Communication Society) SSD84-101 (issued on Dec. 18, 1984). This method is named Multiple Self-Alignment MOS Transistors. However, this method still requires many processes, such as filling gaps between the substrate and side-etched polysilicon film by polysilicon, and isotropic etching.